Are you looking for challenging work and awesome work culture?
ASICtronix has great opportunities for you. We will give you awesome work culture that nourishes talent and empowers everyone to enjoy and excel at work. If you are looking for challenges, freedom, quality and empowerment join us today.
ASICtronix is actively looking for freshers and experienced engineers with following qualifications and skills.
Drop us an email with your resume at careers@asictronix.com
Title: Design Verification Engineer (Entry level)
Minimum Qualification:
You must have a Bachelor of Engineering degree in Electronics, Electrical Engineering.
Knowledge in Digital Logic Design and Computer Architecture.
Coding in at least one language: C, C++ or SystemVerilog.
Strong interpersonal and communication skills.
Must be comfortable working across geographies.
Strong analytical/problem solving skills and pronounced attention to details.
Job Description:
As a Design Verification Engineer, you will be responsible for verifying complex Digital logical Design in a pre-silicon environment.
The Digital Logic Design can be a CPU, SOC, IP, High Speed IO, DDR IP.
Job involves writing complex code to develop and maintain testbench using SystemVerilog/UVM.
Writing testplan based on test scenarios, test cases to create interesting stimulus.
Hands-on verification work including verification regression management, debugging and bug-reports
Communication with peers to discuss technical details
Preferred Skills:
Unix, C, C++, UVM, SystemVerilog, Perl, Python, Assembly Language, Computer Architecture.
Protocol knowledge like: AMBA/High Speed/Netwoking would be advantageous.
Familiarity with PCIE, USB, SATA, SOC.
Location: Bhopal, Madhya Pradesh(Temporarily Remote)
Title: Sr. Design Verification Engineer –
Minimum Qualification:
You must have a B.E or Masters degree in Electronics/Electrical Engineering plus 2 to 4 years of experience working as a Design Verification Engineer.
Knowledge in Digital Logic Design, Computer Architecture, System Verilog, UVM.
Hands-on experience in System Verilog, UVM, Scripting for automation.
Job Description:
As a Design Verification Engineer, you will be responsible for verifying complex Digital logical Design in a pre-silicon environment.
The Digital Logic Design can be a CPU, SOC, IP, High Speed IO, DDR IP.
Job involves writing complex code to develop testbench from scratch using System Verilog/UVM.
Writing testplan based on test scenarios, test cases to create interesting stimulus.
Hands-on verification work including verification regression management, debugging and bug-reports
Communication with peers to discuss technical details.
Provide technical guidance to junior members of the team.
Preferred Skills:
Unix, C, C++, UVM, System Verilog, Perl, Python, Assembly Language, Computer Architecture.
Protocol knowledge like: AMBA/High Speed/Netwoking would be advantageous.
Familiarity with CPU, SOC, DDR IP, High speed IO like PCIE, USB, SATA.
Location: Bhopal, Madhya Pradesh(Temporarily Remote)